A metal oxide semiconductor field effect transistor (MOSFET) is constructed with two electrodes (“source” and “drain”) of one impurity conductivity type formed in a semiconductor substrate of opposite impurity conductivity type and separated by a channel region formed in the semiconductor substrate. The channel region is overlain by a dielectric layer (the “gate dielectric”) on top of the silicon substrate. A gate electrode (“gate”) is formed over the dielectric layer. In an enhancement mode MOSFET (i.e. a MOSFET which conducts a small leakage current between the source and the drain for an applied gate voltage below the MOSFET threshold voltage), when a voltage applied to the gate is over the threshold voltage of the MOSFET, the channel region of the MOSFET is inverted to make full electrical connection between the source and the drain. Non-volatile memory (NVM) cells are constructed by adding material capable of storing charge in the gate dielectric and then placing electrical charge in this material (hereinafter “storing material”) which is located between the gate electrode and the channel region of the MOSFET. The storing material can be a conducting material such as highly doped polysilicon, charge trapping dielectric such as a nitride film, or nanocrystals. By placing charge in the storing material in an NVM cell, the threshold voltage of the MOSFET can be altered. The stored charge represents information to be stored. By varying the amount of charge stored in or on the storing material, the value represented by the charge stored in the storing material can be varied. Variable information (typically in the form of n-bit digital binary words converted to analog signals) can thus be stored in or on the storing material by placing various amounts of charges in or on the storing material to alter different threshold voltage levels of NVM cells. The stored charge in an NVM cell is not volatile even when the power for the NVM is turned off. The information can be retrieved by reading out the stored threshold level of the NVM cell in which the information is stored.
The conventional reading out of the threshold voltage of an NVM cell is done by applying a constant voltage or multiple stepped voltages to the control gate of the NVM cell with the drain electrode connecting to a loading element such as a transistor or a resistor. When a read voltage bias is applied to the loading element connected in series with the NVM cell's drain electrode and the applied NVM's gate voltage is sufficient to turn on the MOSFET in the NVM cell, electrical current thus flows through the load element to and through the NVM cell. The current and the voltage at the node between the NVM cell and the loading element will respond according to the NVM cell threshold voltage and applied gate voltage. In the constant control gate voltage readout scheme, the current flowing through the load element and NVM cell is compared to the current flowing through the same configuration with the load element connected to a referencing NVM cell under the same voltage bias condition. The result of the comparison is applied to determine the stored information in the NVM cell.
In the conventional stepped voltage scheme, various voltages are applied in sequence to the control gate of an NVM cell for reading out. By applying a voltage bias through the load element to the NVM cell, the voltage at the node between the NVM cell and the load element is detected as a function of the applied gate voltage and the cell threshold voltage. The information stored in the NVM cell is then readout when the voltage applied to the gate of the MOSFET in the NVM cell is just sufficient to turn on the MOSFET in the NVM cell. For example, in Samsung's 128 Mb multilevel NAND flash designs (Tae-Sung Jung et. al., IEEE Journal of Solid-State Circuit, Vol. 31, No. 11, November 1996), a P-type transistor as a load element biased with a reference gate voltage is connected to the NAND NVM string. The voltages at the node between the load element and the NAND cell string vary according to the gate voltage applied to the selected cell and the cell's stored threshold voltage level. The various voltages at this node are applied to pull a latch in an output buffer to convert the stored information in the NVM cell into digital format.